Process algebra
Global scheduling independent of control dependencies based on condition vectors
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
High-level synthesis with pin constraints for multiple-chip designs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
VHDL, Hardware Description and Design
VHDL, Hardware Description and Design
Analysis and Synthesis of Concurrent Digital Circuits Using Control-Flow Expressions
Analysis and Synthesis of Concurrent Digital Circuits Using Control-Flow Expressions
Matching system and component behaviour in MIMOLA synthesis tools
EURO-DAC '90 Proceedings of the conference on European design automation
Limited exception modeling and its use in presynthesis optimizations
DAC '97 Proceedings of the 34th annual Design Automation Conference
Scheduling and binding bounds for RT-level symbolic execution
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Efficient encoding for exact symbolic automata-based scheduling
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Scheduling hardware/software systems using symbolic techniques
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
A model for scheduling protocol-constrained components and environments
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Automata-Based Symbolic Scheduling for Looping DFGs
IEEE Transactions on Computers
Adaptive Multiuser Online Reconfigurable Engine
IEEE Design & Test
Symbolic NFA scheduling of a RISC microprocessor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On applicability of symbolic techniques to larger scheduling problems
EDTC '95 Proceedings of the 1995 European conference on Design and Test
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
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We present in this paper a novel control synthesis technique for system-level specifications that are better described as a set of concurrent synchronous descriptions, their synchronizations and constraints. The proposed synthesis technique considers the degrees of freedom introduced by the concurrent models and by the environment in order to satisfy the design constraints.Synthesis is divided in two phases. In the first phase, the original specification is translated into an algebraic system, for which complex control-flow constraints and quantifiers of the design are determined. This algebraic system is then analyzed and the design space of the specification is represented by a finite-state machine, from which a set of Boolean formulas is generated and manipulated in order to obtain a solution. This method contrasts with usual high-level synthesis methods in that it can handle arbitrarily complex control-flow structures, concurrency and synchronization by allowing the scheduling of the operations to change dynamically over time.