Synthesis of pipelined instruction set processors
DAC '93 Proceedings of the 30th international Design Automation Conference
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Efficient encoding for exact symbolic automata-based scheduling
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
ECL: a specification environment for system-level design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Automata-Based Symbolic Scheduling for Looping DFGs
IEEE Transactions on Computers
Synthesis of operation-centric hardware descriptions
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Symbolic Simulation of the JEM1 Microprocessor
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Parallelizing Applications into Silicon
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A new symbolic technique for control-dependent scheduling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scheduling and control generation with environmental constraints based on automata representations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We describe a set of techniques for representing the high-level behavior of a digital subsystem as a collection of nondeterministic finite automata, NFA. Desired behavioral dynamics such as functional dependencies, sequential timing, and sequencing, and control state are similarly modeled. Using techniques similar to that used in formal model checking, we implicitly explore the possible execution sequences of the system, obeying all imposed constraints. This provides a very general, systematic mechanism for performing high-level synthesis of cyclic, control dominated behaviors, constrained by arbitrary sequential constraints. In this paper, we show that these techniques are scalable to practical problem sizes and complexities by constructing a high-level model of a (MIPS IV) RISC Microprocessor and then performing exact scheduling and related design tradeoffs on this model. The model is constructed at the level of register transactions to address the majority of contention and arbitration issues of architectural interest.