Scheduling and binding bounds for RT-level symbolic execution
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Efficient encoding for exact symbolic automata-based scheduling
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A model for scheduling protocol-constrained components and environments
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Automata-Based Symbolic Scheduling for Looping DFGs
IEEE Transactions on Computers
Symbolic NFA scheduling of a RISC microprocessor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Representing and Scheduling Looping Behavior Symbolically
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
| Hi-index | 0.04 |
We introduce a framework for synthesis of behavioral models in which design information is represented using an automaton model. This model offers the advantage of supporting different constraints (e.g., timing, resource, synchronization, etc.) with a uniform formalism. The set of all feasible execution traces (schedules) is constructed and traversed using efficient BDD-based implicit state-traversal techniques. As an application example of this formalism, we present a novel scheduling/control-generation algorithm under environmental constraints where both the design and constraints are represented using automata. We present an algorithm that generates a minimum-latency schedule and a control unit representation. This approach is able to exploit degrees of freedom among interacting components of a multimodule system during scheduling, and is well suited for system-level design, where component encapsulation and interfacing are important