An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper)

• Authors:

• Nozomu Togawa;Masayuki Ienaga;Masao Yanagisawa;Tatsuo Ohtsuki

• Affiliations:

• Dept. of Electronics, Information and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555, Japan;Dept. of Electronics, Information and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555, Japan;Dept. of Electronics, Information and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555, Japan;Dept. of Electronics, Information and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555, Japan

• Venue:
• ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
• Year:
• 2000