Relational algebra as formalism for hardware design
EUROMICRO 93 Nineteenth EUROMICRO symposium on microprocessing and microprogramming on Open system design : hardware, software and applications: hardware, software and applications
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
HDL optimization using timed decision tables
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Behavior tables: a basis for system representation and transformational system synthesis
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
The Verilog hardware description language (4th ed.)
The Verilog hardware description language (4th ed.)
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An Algorithm for Structuring Flowgraphs
Journal of the ACM (JACM)
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
IEEE Design & Test
Decomposition of timed decision tables and its use in presynthesis optimizations
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
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In behavioral descriptions, statementsthat allow limited control jumps, such as Verilog disablestatements on named blocks, are often used for describingsystem behavior in presence of exceptions.In this paper,we extend Timed Decision Tables (TDT), a tabularbehavior model, to represent more general control structuresincluding exceptions.We introduce the notion of action sharing that allows us to reduce resoruce requirementsusing existing high-level synthesis tools on descriptionswith control exceptions.We present presynthesisalgorithms that work on the extended TDT model and analgorithm that performs action sharing in TDT models.Our experiments on well-known HardwareC benchmarksshow size reduction resulting from sharing actions in theinput behavioral descriptions.