High level synthesis of ASICs under timing and synchronization constraints
High level synthesis of ASICs under timing and synchronization constraints
Specification and design of embedded systems
Specification and design of embedded systems
HDL optimization using timed decision tables
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Limited exception modeling and its use in presynthesis optimizations
DAC '97 Proceedings of the 34th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
IEEE Design & Test
HDL code restructuring using timed decision tables
Proceedings of the 6th international workshop on Hardware/software codesign
An algorithm to determine mutually exclusive operations in behavioral descriptions
Proceedings of the conference on Design, automation and test in Europe
Coordinated parallelizing compiler optimizations and high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Presynthesis optimizations transform a behavioral HDL description into an optimized HDL description that results in improved synthesis results. We introduce the decomposition of timed decision tables (TDT), a tabular model of system behavior. The TDT decomposition is based on the kernel extraction algorithm. By experimenting using named benchmarks, we demonstrate how TDT decomposition can be used in presynthesis optimizations.