Register Synthesis for Speculative Computation

Authors:
Dirk Herrmann;Rolf Ernst
Affiliations:
Institute of Computer Engineering, Technical University of Braunschweig, Germany;Institute of Computer Engineering, Technical University of Braunschweig, Germany
Venue:
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Year:
1997

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Abstract

Speculative computation and branch prediction have been used in high-performance processor design for many years. Recently, it has also been applied to high-level synthesis where a priori knowledge of possible control paths provides an even higher performance potential. One problem of speculative techniques is the circuit overhead necessary for correctness preservation. While in processors, overhead is high due to the required generality, high-level synthesis can, again, employ a priori knowledge. The paper presents a register synthesis and allocation technique for speculative computation with branch prediction which is based on life time trees. It creates shift register structures with little register and control overhead.