Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Region Scheduling: An Approach for Detecting and Redistributing Parallelism
IEEE Transactions on Software Engineering
Global scheduling independent of control dependencies based on condition vectors
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Representing conditional branches for high-level synthesis applications
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Limits of control flow on parallelism
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Efficient superscalar performance through boosting
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
An efficient resource-constrained global scheduling technique for superscalar and VLIW processors
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
A tree-based scheduling algorithm for control-dominated circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Global scheduling with code-motions for high-level synthesis applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Time-constrained code compaction for DSPs
ISSS '95 Proceedings of the 8th international symposium on System synthesis
A path-based technique for estimating hardware runtime in HW/SW-cosynthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Efficient orthonormality testing for synthesis with pass-transistor selectors
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Design Automation for Embedded Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A global resource-constrained parallelization technique
ICS '89 Proceedings of the 3rd international conference on Supercomputing
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Making Compaction-Based Parallelization Affordable
IEEE Transactions on Parallel and Distributed Systems
A unified scheduling model for high-level synthesis and code generation
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A Constructive Method for Exploiting Code Motion
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Area and performance optimizations in path-based scheduling
EURO-DAC '91 Proceedings of the conference on European design automation
A new symbolic technique for control-dependent scheduling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automata-Based Symbolic Scheduling for Looping DFGs
IEEE Transactions on Computers
Efficient scheduling of conditional behaviors for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Formal verification of code motion techniques using data-flow-driven equivalence checking
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
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In the high-level synthesis of ASICs or in the code generation for ASIPs, the presence of conditionals in the behavioral description represents an obstacle to exploit parallelism. Most existing methods use greedy choices in such a way that the search space is limited by the applied heuristics. For example, they might miss opportunities to optimize across basic block boundaries when treating conditional execution. We propose a constructive method which allows generalized code motions. Scheduling and code motion are encoded in the form of a unified resource-constrained optimization problem. In our approach many alternative solutions are constructed and explored by a search algorithm, while optimal solutions are kept in the search space. Our method can cope with issues like speculative execution and code such duplication. Moreover, it can tackle constraints imposed by the advance choice of a controller, such as pipelined-control delay and limited branch capabilities. The underlying timing models support chaining and multicycling. As tasking code motion into account may lead to a larger search space, a code-motion pruning technique is presented. This pruning is proven to keep optimal solutions in the search space for cost functions in terms of schedule lengths.