DAC '98 Proceedings of the 35th annual Design Automation Conference
Journal of VLSI Signal Processing Systems - Special issue on system level design
Journal of VLSI Signal Processing Systems - Special issue on the 1997 IEEE workshop on signal processing systems (SiPS): design and implementation
Analysis of high-level address code transformations for programmable processors
DATE '00 Proceedings of the conference on Design, automation and test in Europe
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 14th international symposium on Systems synthesis
Proceedings of the 14th international symposium on Systems synthesis
Data reorganization engines for the next generation of system-on-a-chip FPGAs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Memory management for embedded network applications
Readings in hardware/software co-design
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Practical parallel computing
Address code generation for DSP instruction-set architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Address Code and Arithmetic Optimizations for Embedded Systems
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A Novel Implementation of Tile-Based Address Mapping
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Mesh Partitioning Approach to Energy Efficient Data Layout
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Coordinated parallelizing compiler optimizations and high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Transformation synthesis for data intensive applications to FPGAs
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Address Generation Optimization for Embedded High-Performance Processors: A Survey
Journal of Signal Processing Systems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Journal of Signal Processing Systems
Constructing application-specific memory hierarchies on FPGAs
Transactions on high-performance embedded architectures and compilers III
A design methodology to implement memory accesses in high-level synthesis
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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Data-transfer intensive applications typically contain heavily accessed memories involving considerable arithmetic for the computation and the selection of the different memory access pointers. This data processing, namely addressing, becomes dominant in the overall arithmetic cost and it has to be executed under very tight timing constraints. Different high-level optimizing alternatives suitable for addressing are explored in our Adopt methodology and prototype tool environment to reduce the addressing overhead. They include address expression splitting/clustering, induction variable analysis, target architecture selection, and global-scope algebraic optimization. In addition, some steps aiming to reduce at the system level the time-multiplexed address unit cost, are also incorporated for area and power efficiency. The techniques are demonstrated on test-vehicles representative of real-life applications, shelving important savings on the overall arithmetic cost.