High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
High level synthesis of ASICs under timing and synchronization constraints
High level synthesis of ASICs under timing and synchronization constraints
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming
EURO-DAC '94 Proceedings of the conference on European design automation
Clock-driven performance optimization in interactive behavioral synthesis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Principles of digital design
System Design with SystemC
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
System Design: A Practical Guide with Specc
System Design: A Practical Guide with Specc
Defining an Enhanced RTL Semantics
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
C-based SoC design flow and EDA tools: an ASIC and system vendor perspective
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-on-chip environment: a SpecC-based framework for heterogeneous MPSoC design
EURASIP Journal on Embedded Systems - C-Based Design of Heterogeneous Embedded Systems
Towards a tighter integration of generated and custom-made hardware
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
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Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of control on RTL design, push-button type synthesis is not accepted by many designers. Interactive design with assistance of algorithms and tools can be more effective if it provides control to the steps of synthesis. In this paper, we propose an interactive RTL design environment which enables designers to control the design steps and to integrate hardware components into a system. Our design environment is targeting a generic RTL processor architecture and supporting pipelining, multicycling, and chaining. Tasks in the RTL design process include clock definition, component allocation, scheduling, binding, and validation. In our interactive environment, the user can control the design process at every stage, observe the effects of design decisions, and manually override synthesis decisions at will. We present a set of experimental results that demonstrate the benefits of our approach. Our combination of automated tools and interactive control by the designer results in quickly generated RTL designs with better performance than fully-automatic results, comparable to fully manually optimized designs.