Design experience of a chip multiprocessor merlot and expectation to functional verification
Proceedings of the 15th international symposium on System Synthesis
Interface synthesis between software chip model and target board
Journal of Systems Architecture: the EUROMICRO Journal
C-based behavioral synthesis and verification analysis on industrial design examples
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
SystemC Modeling of a Bluetooth Transceiver: Dynamic Management of Packet Type in a Noisy Channel
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
SOFTENIT: a methodology for boosting the software content of system-on-chip designs
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Power estimation for cycle-accurate functional descriptions of hardware
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Hardware/software partitioning of operating systems: a behavioral synthesis approach
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
The Challenges of Synthesizing Hardware from C-Like Languages
IEEE Design & Test
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Mapping streaming architectures on reconfigurable platforms
ACM SIGARCH Computer Architecture News - Special issue on the 2006 reconfigurable and adaptive architecture workshop
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
An interactive design environment for C-based high-level synthesis of RTL processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new methodology of integrating high level synthesis and floorplan for soc design
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
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This paper examines the achievements and future of system-on-a-chip (SoC) design methodology and design flow from the viewpoints of an in-house electronic design automation team of an application-specific integrated circuit and system vendor. We initially discuss the problems of the design productivity gap caused by the SoC's complexity and the timing closure caused by deep-submicrometer technology. To solve these two problems, we propose a C-based SoC design environment that features integrated high-level synthesis (HLS) and verification tools. A HLS system is introduced using various successful industrial design examples, and its advantages and drawbacks are discussed. We then look at the future directions of this system. The high-level verification environment consists of a mixed-level hardware/software co-simulator, formal and semi-formal verifiers, and test-bench generators. The verification tools are tightly integrated with the HLS system and take advantage of information from the synthesis system. Then, we discusses the possibility of incorporating physical design features into the C-based SoC design environment. Finally, we describe our global vision for an SoC architecture and SoC design methodology