Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study

Authors:
Yuko Hara;Hiroyuki Tomiyama;Shinya Honda;Hiroaki Takada;Katsuya Ishii
Affiliations:
Graduate School of Information Science, Nagoya University,;Graduate School of Information Science, Nagoya University,;Graduate School of Information Science, Nagoya University,;Graduate School of Information Science, Nagoya University,;Information Technology Center, Nagoya University, Furo-cho, Chikusa-ku, Nagoya, 464-8603, Japan
Venue:
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Year:
2007

Citing 2
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Abstract

Recently, the continuously growing capacity of FPGAs has enabled us to place floating-point arithmetic IPs on FPGAs. The required area for floating-point computations, however, is still high. This paper presents a case study on behavioral synthesis of double-precision floating-point adders and adder/subtracters for FPGAs. With function-level transformations, we design totally 15 adders and 21 adder/subtracters from addition and subtraction functions written in C. Our experimental results show that the circuit area is reduced by 58%, the execution time is shortened by 47% and the area-delay product is improved by 69%. Through the case study, we show the effectiveness of behavioral synthesis with function-level transformations for designing complex arithmetic circuits.