Model composition for scheduling analysis in platform design
Proceedings of the 39th annual Design Automation Conference
Analyzing Infeasible Mixed-Integer and Integer Linear Programs
INFORMS Journal on Computing
AMUSE: a minimally-unsatisfiable subformula extractor
Proceedings of the 41st annual Design Automation Conference
A General Framework for Analysing System Properties in Platform-Based Embedded System Designs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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RTSS '04 Proceedings of the 25th IEEE International Real-Time Systems Symposium
Period optimization for hard real-time distributed automotive systems
Proceedings of the 44th annual Design Automation Conference
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Specify-explore-refine (SER): from specification to implementation
Proceedings of the 45th annual Design Automation Conference
WCET-aware register allocation based on graph coloring
Proceedings of the 46th Annual Design Automation Conference
Scheduling the FlexRay bus using optimization techniques
Proceedings of the 46th Annual Design Automation Conference
Combined system synthesis and communication architecture exploration for MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Improving platform-based system synthesis by satisfiability modulo theories solving
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Symbolic system synthesis in the presence of stringent real-time constraints
Proceedings of the 48th Design Automation Conference
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This paper presents a methodology for the concurrent optimization of the architecture and scheduling of upcoming synchronous time-triggered automotive systems. A fully synchronous time-triggered system is highly predictable and therefore the best candidate for safety and drive-by-wire functions with strict real-time constraints. While the architecture of these systems has to be optimized in terms of resource allocation, task mapping, and message routing by taking multiple conflicting objectives into account, the scheduling has to be carried out such that application deadlines are satisfied. In case of stringent real-time constraints, available approaches that address architecture optimization and scheduling as separate problems become inapplicable as most architectures do not permit a feasible schedule. As a remedy, a novel and efficient approach based on conflict refinement is presented. For a given architecture, either a schedule might be obtained or a conflict refinement is performed to determine and exclude the architecture decision that prevents a feasible schedule. In this paper, an extended architecture model is presented and the scheduling and refinement approaches are given for time-triggered architectures based on the FlexRay protocol. This approach can be extended to other protocols and scenarios. A case study of a realistic time-triggered system gives evidence of the efficiency of the proposed approach, solving a large design problem from the automotive domain.