Compiling Global Name-Space Parallel Loops for Distributed Execution
IEEE Transactions on Parallel and Distributed Systems
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Design and programming of embedded multiprocessors: an interface-centric approach
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Overview of the MPSoC design challenge
Proceedings of the 43rd annual Design Automation Conference
Programming models and HW-SW interfaces abstraction for multi-processor SoC
Proceedings of the 43rd annual Design Automation Conference
An RTOS API Translator for Model-Driven Embedded Software Development
RTCSA '06 Proceedings of the 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
Hardware-Software Codesign of Multimedia Embedded Systems: the PeaCE
RTCSA '06 Proceedings of the 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
Model-based Programming Environment of Embedded Software for MPSoC
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Effective OpenMP Implementation and Translation For Multiprocessor System-On-Chip without Using OS
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
A practical OpenMP compiler for system on chips
WOMPAT'03 Proceedings of the OpenMP applications and tools 2003 international conference on OpenMP shared memory parallel programming
A high-level virtual platform for early MPSoC software development
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Adaptive scratch pad memory management for dynamic behavior of multimedia applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Electronic system-level synthesis methodologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Versatile system-level memory-aware platform description approach for embedded MPSoCs
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms
Proceedings of the Conference on Design, Automation and Test in Europe
Programming MPSoC platforms: road works ahead!
Proceedings of the Conference on Design, Automation and Test in Europe
Improving platform-based system synthesis by satisfiability modulo theories solving
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
MPSoC programming using the MAPS compiler
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Energy-efficient scheduling for parallel real-time tasks based on level-packing
Proceedings of the 2011 ACM Symposium on Applied Computing
Symbolic system synthesis in the presence of stringent real-time constraints
Proceedings of the 48th Design Automation Conference
A middleware approach to achieving fault tolerance of Kahn process networks on networks on chips
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
Proceedings of the 9th conference on Computing Frontiers
Automatic CUDA code synthesis framework for multicore CPU and GPU architectures
PPAM'11 Proceedings of the 9th international conference on Parallel Processing and Applied Mathematics - Volume Part I
A rule-based quasi-static scheduling approach for static islands in dynamic dataflow graphs
ACM Transactions on Embedded Computing Systems (TECS)
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As more processing elements are integrated in a single chip, embedded software design becomes more challenging: It becomes a parallel programming for nontrivial heterogeneous multiprocessors with diverse communication architectures, and design constraints such as hardware cost, power, and timeliness. In the current practice of parallel programming with MPI or OpenMP, the programmer should manually optimize the parallel code for each target architecture and for the design constraints. Thus, the design-space exploration of MPSoC (multiprocessor systems-on-chip) costs become prohibitively large as software development overhead increases drastically. To solve this problem, we develop a parallel-programming framework based on a novel programming model called common intermediate code (CIC). In a CIC, functional parallelism and data parallelism of application tasks are specified independently of the target architecture and design constraints. Then, the CIC translator translates the CIC into the final parallel code, considering the target architecture and design constraints to make the CIC retargetable. Experiments with preliminary examples, including the H.263 decoder, show that the proposed parallel-programming framework increases the design productivity of MPSoC software significantly.