Partitioning and pipelining for performance-constrained hardware/software systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Network-on-Chip Modeling for System-Level Multiprocessor Simulation
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Proceedings of the conference on Design, automation and test in Europe - Volume 1
System-Level Design Techniques for Energy-Efficient Embedded Systems
System-Level Design Techniques for Energy-Efficient Embedded Systems
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A SystemC Refinement Methodology for Embedded Software
IEEE Design & Test
Hardware-Software Codesign of Multimedia Embedded Systems: the PeaCE
RTCSA '06 Proceedings of the 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
PeaCE: A hardware-software codesign environment for multimedia embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Mapping Applications to Tiled Multiprocessor Embedded Systems
ACSD '07 Proceedings of the Seventh International Conference on Application of Concurrency to System Design
NoC Topologies Exploration based on Mapping and Simulation Models
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Muiltiobjective optimization using nondominated sorting in genetic algorithms
Evolutionary Computation
Optimizing Configuration and Application Mapping for MPSoC Architectures
AHS '09 Proceedings of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems
Reducing the run-time complexity of multiobjective EAs: The NSGA-II and other algorithms
IEEE Transactions on Evolutionary Computation
IEEE Transactions on Evolutionary Computation
Design space exploration for optimizing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Online task remapping strategies for fault-tolerant Network-on-Chip multiprocessors
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Partitioning and mapping on NoC-Based MPSoC: an energy consumption saving approach
Proceedings of the 4th International Workshop on Network on Chip Architectures
A3MAP: Architecture-aware analytic mapping for networks-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Formal approach to agent-based dynamic reconfiguration in Networks-On-Chip
Journal of Systems Architecture: the EUROMICRO Journal
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Networks on Chip (NoC) have emerged as the key paradigm for designing a scalable communication infrastructure for future Systems on Chip (SoC). An important issue in NoC design is how to map an application on this architecture and how to determine the hardware/software partition that satisfies the performance, cost and flexibility requirements. In this paper, we propose an approach that concurrently optimizes the mapping and the partitioning of streaming applications. The proposed approach exploits multiobjective evolutionary algorithms that are fed by execution performances scores corresponding to the evaluated mappings and partitioning ability to pipeline execution of the streaming application. As result, most promising solutions are highlighted for mapping multimedia applications onto a SoC architecture interconnecting 16 nodes through 2D-Mesh and Ring NoC.