Combining mapping and partitioning exploration for NoC-based embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
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Networks on Chip (NoCs) have emerged as the key paradigm for designing a scalable communication infrastructure for future Multi-Processors Systems on Chip(MPSoCs). An important issue in NoC design is how to configure a NoC-based architecture and how to map an application on this architecture in order to satisfy the performance and cost requirements. In this paper, we propose an approach that concurrently optimizes the configuration of NoC-based architectures and the mapping of streaming applications. The proposed approach exploits multiobjective evolutionary algorithms that are fed by execution performances scores corresponding to the evaluated MPSoC configurations and mappings ability to pipeline execution of the streaming application. As an optimization result, most promising configurations and mappings are highlighted. We show results for mapping an image processing application onto a configurable MPSoC architecture. These results highlight MPSoC architectures configured to interconnect up to 12 processors using Crossbar, Mesh and Ring topologies.