Compiling Scilab to high performance embedded multicore systems
Microprocessors & Microsystems
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Reconfigurable tile-based architectures can dynamically interconnect several tiles in order to establish processor instances with varying resource, performance, and energy characteristics at run time. These flexible processor instances offer a new degree of freedom for adapting to changing applications' requirements while optimizing resource and energy consumption. Our solution for dynamic interconnection of tiles requires a flexible Run-Time Scalable Issue-Width (RSIW) Instruction Set Architecture (ISA) that changes dependent on the configuration. In order to enable high-level programmability of our architecture in C/C++ a novel compiler back-end is needed. In this paper we address this necessity by presenting a novel LLVM compiler back-end targeting the reconfigurable RSIW ISA and supporting mixed-ISA software development. RSIW is comparable to clustered-VLIW ISAs since it expresses parallel operations within the ISA and explicitly uses clustered register files. Therefore, we extended our architecture description language based RISC LLVM back-end by representations of parallel operations as well as compilation passes for clustering and scheduling of parallel operations as well as mixed-ISA code generation. Based on the novel back-end we compare the performance characteristics of several applications compiled for and simulated on different configurations. Additionally, we demonstrate resource-aware reconfiguration by a mixed-ISA application scenario.