Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Force-directed scheduling in automatic data path synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Synthesis using path-based scheduling: algorithms and exercises
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Solving the incremental satisfiability problem
Journal of Logic Programming
Resolution for quantified Boolean formulas
Information and Computation
Scheduling using behavioral templates
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
GRASP—a new search algorithm for satisfiability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Estimation of lower bounds in scheduling algorithms for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
A machine program for theorem-proving
Communications of the ACM
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Computers and Intractability; A Guide to the Theory of NP-Completeness
Computers and Intractability; A Guide to the Theory of NP-Completeness
A symbolic approach for the combined solution of scheduling and allocation
Proceedings of the 15th international symposium on System Synthesis
Fast Prototyping of Datapath-Intensive Architectures
IEEE Design & Test
LCPC '96 Proceedings of the 9th International Workshop on Languages and Compilers for Parallel Computing
Lower bound estimation of hardware resources for scheduling in high-level synthesis
Journal of Computer Science and Technology
Accurate Resource Estimation Algorithms for Behavioral Synthesis
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Accelerated SAT-based Scheduling of Control/Data Flow Graphs
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Counterexample-guided abstraction refinement for symbolic model checking
Journal of the ACM (JACM)
Automata-based symbolic scheduling
Automata-based symbolic scheduling
Towards a global solution to high level synthesis problems
EURO-DAC '90 Proceedings of the conference on European design automation
Efficient SAT solving under assumptions
SAT'12 Proceedings of the 15th international conference on Theory and Applications of Satisfiability Testing
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Hardware synthesis is the process by which system-level, Register Transfer (RT)-level, or behavioral descriptions can be turned into real implementations, in terms of logic gates. Scheduling is one of the most time-consuming steps in the overall design flow, and may become much more complex when performing hardware synthesis from high-level specifications. Exploiting a single scheduling strategy on very large designs is often reductive and potentially inadequate. Furthermore, finding the “best” single candidate among all possible scheduling algorithms is practically infeasible. In this article we introduce a hybrid scheduling approach that is a preliminary step towards a comprehensive solution not yet provided by industrial or by academic solutions. Our method relies on an abstract symbolic representation of data flow nodes (operations) bound to control flow paths: it produces a more realistic lower bound during the prescheduling resource estimation step and speeds up slower but accurate heuristic scheduling techniques, thus achieving a globally improved result.