RTL Synthesis with Physical and Controller Information

Authors:
Min Xu;Fadi Kurdahi
Affiliations:
Department of Information. and Computer Science, University of California, Irvine, CA;Department of Electrical & Computer Engineering, University of California, Irvine, CA
Venue:
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Year:
1997

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Abstract

The current technology advances towards deep submicron have made it indispensable to consider layout and controller effects during all phases of chip synthesis. This paper proposes a paradigm for incorporating such information when synthesizing an RTL design from a scheduled behavioral specification. Experimental results corroborate the fact that layout and controller effects on chip area and performance are significant and can not be ignored.