Force-directed scheduling in automatic data path synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Controller estimation for FPGA target architectures during high-level synthesis
Proceedings of the 15th international symposium on System Synthesis
A Fast and Effective Algorithm for the Feedback Arc Set Problem
Journal of Heuristics
RTL Synthesis with Physical and Controller Information
EDTC '97 Proceedings of the 1997 European conference on Design and Test
How Many CLBs Does Your Circuit Need to be Implemented?
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
Rapid estimation of control delay from high-level specifications
Proceedings of the 43rd annual Design Automation Conference
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A procedure for estimating the complexity of synthesized designs from finite-state machine (FSM) specifications is described. Incorporating this estimate in the data path synthesis stage allows a trade-off between data path and control logic, resulting in high quality designs in terms of synthesized logic area. It is shown that the estimation process takes 650 to 3000 times less CPU time than the synthesis procedure.