Accurate layout area and delay modeling for system level design
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Simultaneous functional-unit binding and floorplanning
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
SMASH: a program for scheduling memory-intensive application-specific hardware
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
A grid-based approach for connectivity binding with geometric costs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Area and Timing Estimation for Lookup Table Based FPGAs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Soft scheduling in high level synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Architecture and synthesis for multi-cycle communication
Proceedings of the 2003 international symposium on Physical design
RTL Synthesis with Physical and Controller Information
EDTC '97 Proceedings of the 1997 European conference on Design and Test
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The importance of effective and efficient accounting of layout effects is well-established in high-level synthesis (HLS), since it allows more realistic exploration of the design space and the generation of solutions with predictable metrics. This feature is highly desirable in order to avoid unnecessary iterations through the design process. In this paper, we address the problem of layout-driven register-transfer-level (RTL) binding as this step has a direct relevance on the final performance of the design. By producing not only an RTL design but also an approximate physical topology of the chip level implementation, we ensure that the solution will perform at the predicted metric once implemented, thus avoiding unnecessary delays in the design process.