Soft scheduling in high level synthesis

Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

Instruction level parallelism of non-uniform acyclic loops

Journal of Computing Sciences in Colleges

A cycle-accurate compilation algorithm for custom pipelined datapaths

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Arrival time aware scheduling to minimize clock cycle length

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Performance-driven read-after-write dependencies softening in high-level synthesis

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Pre-synthesis optimization of multiplications to improve circuit performance

Proceedings of the conference on Design, automation and test in Europe: Proceedings

Area optimization of multi-cycle operators in high-level synthesis

Proceedings of the conference on Design, automation and test in Europe

Performance-driven scheduling of behavioural specifications

Integration, the VLSI Journal

Scheduling with soft constraints

Proceedings of the 2009 International Conference on Computer-Aided Design

Register pressure aware scheduling for high level synthesis

Proceedings of the 16th Asia and South Pacific Design Automation Conference