Integer and combinatorial optimization
Integer and combinatorial optimization
Move frame scheduling and mixed scheduling-allocation for the automated synthesis of digital systems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Comprehensive lower bound estimation from behavioral descriptions
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Register assignment through resource classification for ASIP microcode generation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming
EURO-DAC '94 Proceedings of the conference on European design automation
Generating several solutions for the scheduling problem in high-level synthesis
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
A comprehensive estimation technique for high-level synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
A recursive technique for computing lower-bound performance of schedules
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A scheduling method by stepwise expansion in high-level synthesis
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Soft scheduling in high level synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Watermarking integer linear programming solutions
Proceedings of the 39th annual Design Automation Conference
An Enhanced Genetic Solution for Scheduling, Module Allocation, and Binding in VLSI Design
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Storage requirement estimation for optimized design of data intensive applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scheduling under resource constraints using dis-equations
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Fast memory footprint estimation based on maximal dependency vector calculation
Proceedings of the conference on Design, automation and test in Europe
Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications
Journal of Signal Processing Systems
An integrated approach to thermal management in high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal integrated VLIW code generation with integer linear programming
Euro-Par'06 Proceedings of the 12th international conference on Parallel Processing
Constraint-Based register allocation and instruction scheduling
CP'12 Proceedings of the 18th international conference on Principles and Practice of Constraint Programming
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An integer programming (IP) model, which simultaneouslyschedules and allocates functional units, registers, and busses, ispresented for synthesizing cost-constrained globally optimalarchitectures. This research is important for industry by providingoptimal schedules which minimize interconnect costs and interfaceto analog and asynchronous processes, since these are seen as keyto synthesizing high performance architectures. A partiallystructured tight IP formulation of the architectural synthesisproblem provides globally optimal schedules for peicewise linearcost functions, using branch and bound, in execution times fasterthan previous research. This research breaks new ground by 1.simultaneously scheduling and allocating hardware resourcesincluding interconnect, 2. support for asynchronous and analoginterfaces, and 3. guaranteeing globally optimal solutions inpractical execution times.