Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Resource-Constrained Software Pipelining
IEEE Transactions on Parallel and Distributed Systems
Soft scheduling in high level synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
ICPADS '00 Proceedings of the Seventh International Conference on Parallel and Distributed Systems
High-level synthesis of DSP applications using adaptive negative cycle detection
EURASIP Journal on Applied Signal Processing
Retiming synchronous data-flow graphs to reduce execution time
IEEE Transactions on Signal Processing
RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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New applications involving multi-rate systems, data compression and mathematical series, require high computational power, which most of the time implies the use of parallel processing. When the parallelism is associated with super-scalar architectures, code optimization must be applied at the instruction level in order to produce the desired performance. These improvements are usually applied to loop constructs due to their recurrence and criticality in the behavior of the application. Loop optimization has been studied for a very long time and, presently, it is still a complex subject to discuss in the classroom. In this study, the retiming theory is revisited and extended to the case of non-uniform one-dimensional acyclic loops with linear index expressions. The paper provides a new dimension in the study of this loop optimization technique.