MILAN: A Model Based Integrated Simulation Framework for Design of Embedded Systems
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
A compiler approach to fast hardware design space exploration in FPGA-based systems
PLDI '02 Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Accurate Area and Delay Estimators for FPGAs
Proceedings of the conference on Design, automation and test in Europe
Journal of Embedded Computing - Cache exploitation in embedded systems
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
High-Level Synthesis: from Algorithm to Digital Circuit
High-Level Synthesis: from Algorithm to Digital Circuit
An Introduction to High-Level Synthesis
IEEE Design & Test
Designing Modular Hardware Accelerators in C with ROCCC 2.0
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Novo-G: At the Forefront of Scalable Reconfigurable Supercomputing
Computing in Science and Engineering
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
ISVLSI '11 Proceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI
Run-time generation of partial FPGA configurations
Journal of Systems Architecture: the EUROMICRO Journal
Platform-based design from parallel C specifications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
COMPLEX: COdesign and Power Management in PLatform-Based Design Space EXploration
DSD '12 Proceedings of the 2012 15th Euromicro Conference on Digital System Design
| Hi-index | 0.00 |
The very high computing capacity available in the latest Field Programmable Gate Array (FPGA) components allows to extend their application fields, in High-Performance Computing (HPC) as well as in embedded applications. This paper presents a new methodology for Design Space Exploration (DSE) in the context of High-Level Synthesis (HLS) for HPC and embedded systems targeting FPGAs. This new methodology provides very quickly an RTL description of the design under resources constraints. An autonomous flow is described, that performs incremental transformations of the input design description. The low complexity of the transformation evaluation, decision and exploration algorithms, associated with a greedy progression, makes this DSE methodology very fast. Moreover, this methodology respects a strict resource constraint given as bare FPGA primitive amounts. Hence, the generated design fits into the targeted FPGA or a partition of it. Such a methodology leads to autonomous, fast and transparent DSE, all these issues known to limit the use of HLS. Results on several benchmarks highlight the capabilities of our DSE methodology. The results show a high generation time speed-up compared to one other existing HLS approach, while preserving correct performance of the generated circuits.