The Chinook hardware/software co-synthesis system
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Communication synthesis for distributed embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Protocol selection and interface generation for HW-SW codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CoWare—a design environment for heterogenous hardware/software systems
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
A C-based synthesis system, Bach, and its application (invited talk)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Interface Optimization During Hardware-Software Partitioning
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
A modular simulation framework for architectural exploration of on-chip interconnection networks
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Extending the transaction level modeling approach for fast communication architecture exploration
Proceedings of the 41st annual Design Automation Conference
Heterogeneous MP-SoC: the solution to energy-efficient signal processing
Proceedings of the 41st annual Design Automation Conference
Fast exploration of bus-based on-chip communication architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A Network Traffic Generator Model for Fast Network-on-Chip Simulation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Constraint-driven bus matrix synthesis for MPSoC
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Exploiting TLM and object introspection for system-level simulation
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A systematic IP and bus subsystem modeling for platform-based system design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Fast exploration of bus-based communication architectures at the CCATB abstraction
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Multi-layer bus minimization for SoC
Journal of Systems and Software
TLM automation for multi-core design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
EPIDETOX: an ESL platform for integrated circuit design and tool exploration
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
| Hi-index | 0.00 |
For multimedia applications, the System LSI design trend is to integrate an increasing number of applications running on a single chip. Traditional architectures have reached their limit in terms of performance. New architectures must be explored to fulfill the system application needs. Complex bus structures have been introduced. These bus architectures open a much larger exploration space than traditional hardware-software partitioning trade-offs. We have been researching methods to leverage these new architectural elements. We also introduce a design environment to apply practical and efficient methods in todayýs design flow. Two key technologies are supporting our method and environment: Automatic bus architecture synthesis for easy configuration of bus architecture and transaction level of abstraction for communication for improvement of simulation performance. In this paper, we show the design method, an overview of the design environment and its usefulness through experimental results.