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A universal technique for fast and flexible instruction-set architecture simulation
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A Heterogeneous Multiprocessor Architecture for Flexible Media Processing
IEEE Design & Test
Architecture Exploration for Embedded Processors with Lisa
Architecture Exploration for Embedded Processors with Lisa
An IDF-based trace transformation method for communication refinement
Proceedings of the 40th annual Design Automation Conference
System-on-chip beyond the nanometer wall
Proceedings of the 40th annual Design Automation Conference
Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Networks on Silicon: Combining Best-Effort and Guaranteed Services
Proceedings of the conference on Design, automation and test in Europe
Software for multiprocessor networks on chip
Networks on chip
A modular simulation framework for architectural exploration of on-chip interconnection networks
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Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Unified Component Integration Flow for Multi-Processor SoC Design and Validation
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Design of Energy-Efficient Application-Specific Instruction Set Processors
Design of Energy-Efficient Application-Specific Instruction Set Processors
A Practical Approach for Bus Architecture Optimization at Transaction Level
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hardware scheduling support in SMP architectures
Proceedings of the conference on Design, automation and test in Europe
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To meet conflicting flexibility, performance and cost constraints of demanding signal processing applications, future designs in this domain will contain an increasing number of application specific programmable units combined with complex communication and memory infrastructures. Novel architecture trends like Application Specific Instruction-set Processors (ASIPs) as well as customized buses and Network-on-Chip based communication promise enormous potential for optimization. However, state-of-the-art tooling and design practice is not in a shape to take advantage of this advances in computer architecture and silicon technology. Currently, EDA industry develops two diverging strategies to cope with the design complexity of such application specific, heterogeneous MP-SoC platforms. First, the IP-driven approach emphasizes the composition of MP-SoC platforms from configurable off-the-shelf Intellectual Property blocks. On the other hand, the design-driven approach strives to take design efficiency to the required level by use of system level design methodologies and IP generation tools. In this paper, we discuss technical and economical aspects of both strategies. Based on the analysis of recent trends in computer architecture and system level design, we envision a hand-in-hand approach of signal processing platform architectures and design metholodgy to conquer the complexity crisis in emerging MP-SoC developments.