Statistical estimation of the switching activity in digital circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Clock gating for power optimization in ASIC design cycle theory & practice
Proceedings of the 13th international symposium on Low power electronics and design
Automatic synthesis of low-power gated-clock finite-state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analytical models for RTL power estimation of combinational and sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-pass filter for computing the transition density in digital circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Power has become the overriding concern for most modern electronic applications today. To reduce clock power, sequential clock gating is increasingly getting used over and above combinational clock gating. Given the complexity of manually identifying sequential clock gating changes, automatic tools are becoming popular. However, since these tools always work within the scope of the design and the constraints provided, they do not provide any insight into additional power savings that might still be possible. In this paper we present an interactive sequential analysis flow, PowerAdviser, which besides performing automatic sequential changes also provides information for additional power savings that the user can realize through manual changes. Using this new flow we have achieved dynamic power reduction upto 45% more than a purely automated flow.