Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Efficient RTL Power Estimation for Large Designs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A multi-model power estimation engine for accuracy optimization
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Empirical method based on neural networks for analog power modeling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A multi-model engine for high-level power estimation accuracy optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power estimation of CMOS circuits by neural network macromodel
ISNN'06 Proceedings of the Third international conference on Advances in Neural Networks - Volume Part III
PowerAdviser: an RTL power platform for interactive sequential optimizations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we propose a modeling technique that captures the dependence of the power dissipation of a (combinational or sequential) logic circuit on its input/output signal switching statistics. The resulting power macromodel consists of a quadratic or cubic equation in four variables, that can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a low-level (typically gate-level) description of the circuit, we describe a characterization process that uses a recursive least squares (RLS) algorithm by which such an equation-based model can be automatically built. This approach has been implemented and models have been built and tested for many combinational and sequential benchmark circuits