A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Power modeling for high-level power estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analytical macromodeling for high-level power estimation
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Neural Networks: A Comprehensive Foundation
Neural Networks: A Comprehensive Foundation
Lookup Table Power Macro-Models for Behavioral Library Components
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
Stratified random sampling for power estimation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analytical models for RTL power estimation of combinational and sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Markov chain sequence generator for power macromodeling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Neural network is employed to construct the power macromodel of complementary metal-oxide-semiconductor (CMOS) integrated circuits. In contrast to previous modeling approaches, it does not require empirically constructed specialized analytical equations for the power macromodel, and obtained statistics of a circuit’s primary outputs simultaneously. It is suitable for power estimation in core-based systems-on-chips (SoCs) with pre-designed blocks. In experiments with the ISCAS-85 circuits, the average absolute relative error of the macromodel was below 5.0% for not only the average power dissipation, but also the maximum power dissipation.