Low power realization of finite state machines—a decomposition approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Genetic algorithms for VLSI design, layout & test automation
Genetic algorithms for VLSI design, layout & test automation
FSM decomposition by direct circuit manipulation applied to low power design
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Automatic synthesis of low-power gated-clock finite-state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power state assignment targeting two- and multilevel logic implementations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A bipartition-codec architecture to reduce power in pipelined circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power state encoding for partitioned FSMs with mixed synchronous/asynchronous state memory
Integration, the VLSI Journal
Genetic algorithm-based FSM synthesis with area-power trade-offs
Integration, the VLSI Journal
Low power finite state machine synthesis using power-gating
Integration, the VLSI Journal
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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Partitioning has been shown to be an effectivemethod for synthesis of low power finite state machines.In this approach, an FSM is partitioned into two ormore coupled sub-machines such that most of the timeonly one of the sub-machines is active. In this paper,we present a GA based approach for simultaneous partitioning and state assignment of finite state machineswith power reduction as the objective. Experimental results obtained compare favorably with previous works onFSM partitioning, low power state assignment as wellas using GA for partitioning alone.