PowerPC 603 microprocessor power management
Communications of the ACM
Logic synthesis
Precomputation-based sequential logic optimization for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
A survey of optimization techniques targeting low power VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Transformation and synthesis of FSMs for low-power gated-clock implementation
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Guarded evaluation: pushing power management to logic synthesis/design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Low Power Digital CMOS Design
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Logic Synthesis and Verification
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Power-aware clock tree planning
Proceedings of the 2004 international symposium on Physical design
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Gated clocks allow significant power savings in synchronous systems, but are generally considered an unsafe design practice because they decrease testability. In this paper we present two methodologies that guarantee full single-stuck-at testability for gated-clock finite-state machines. The first technique, increased observability, can be used in conjunction with redundancy-removal techniques to obtain fully-testable gated clock FSMs with high performance. The second technique, increased observability and controllability, is applicable to large FSMs for which redundancy removal is not possible and produces fully-testable gated-clock FSMs with a moderate decrease in performance.