Collapsing the transistor chain to an effective single equivalent transistor
Proceedings of the conference on Design, automation and test in Europe
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
CMOS Structures Suitable for Secured Hardware
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Design and Analysis of Dual-Rail Circuits for Security Applications
IEEE Transactions on Computers
Delay Insensitive Encoding and Power Analysis: A Balancing Act
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Automatic synthesis of asynchronous circuits from high-level specifications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Transition time modeling in deep submicron CMOS
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MTD3L: a secure IC design methodology with reduced overhead
ACMIN'12 Proceedings of the 14th international conference on Automatic Control, Modelling & Simulation, and Proceedings of the 11th international conference on Microelectronics, Nanoelectronics, Optoelectronics
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Dual rail logic is considered as a relevant hardware countermeasure against Differential Power Analysis (DPA) by making power consumption data independent. In this paper, we deduce from a thorough analysis of the robustness of dual rail logic against DPA the design range in which it can be considered as effectively robust. Surprisingly this secure design range is quite narrow. We therefore propose the use of an improved logic, called Secure Triple Track Logic, as an alternative to more conventional dual rail logics. To validate the claimed benefits of the logic introduced herein, we have implemented a sensitive block of the Data Encryption Standard algorithm (DES) and carried out by simulation DPA attacks.