Design of Asynchronous Circuits Using Synchronous CAD Tools
IEEE Design & Test
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Speedup of Self-Timed Digital Systems Using Early Completion
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Designing Asynchronous Circuits using NULL Convention Logic (NCL)
Designing Asynchronous Circuits using NULL Convention Logic (NCL)
Analysis and improvement of dual rail logic as a countermeasure against DPA
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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With the increasing use of portable devices containing secure information, side-channel attack (SCA) has become an important threat to hardware. Traditional circuit designs leave otherwise secure systems vulnerable due to the external characteristics of the circuits, rather than in the crypto algorithms themselves. These characteristics are exploitable because they can be easily measured and processed to giving an attacker insight into the device's secret data. Alternative design techniques such as dual-rail asynchronous logic are capable of alleviating this problem to some extent; but still leave exploitable weaknesses while inducing high overhead. Multi-Threshold Dual-spacer Dual-rail Delay-insensitive Logic (MTD3L), presented in this paper, guarantees the security against power-based SCAs by balancing switching activities between the two rails of each signal, while offering a significant reduction in overhead through the incorporation of Multi-Threshold CMOS power gating structure. The SCA mitigating effectiveness and efficiency of MTD3L have been demonstrated by the design and simulation of Advanced Encryption Standard (AES) cores.