Delay estimation and sizing of CMOS logic using logical effort with slope correction

Authors:
Cheng C. Wang;Dejan Markovic
Affiliations:
Department of Electrical Engineering, University of California, Los Angeles, CA;Department of Electrical Engineering, University of California, Los Angeles, CA
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2009

Citing 4
Cited 0

Logical effort: designing fast CMOS circuits

Logical effort: designing fast CMOS circuits
Delay analysis of CMOS gates using modified logical effort model

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Logical effort model extension to propagation delay representation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This brief presents an improved logical-effort model to account for the slope mismatch between the input and output of a gate. The model has a simple formulation in which only one additional parameter is needed, making the analysis suitable for hand calculations. Using 65- and 90-nm complementary metal-oxide-semiconductor technologies, the model maintains less than 5% error in gate-delay estimations compared to Spectre simulations even under large variations between the input and output slopes. Using this model, a circuit optimization tool is written to optimize an adder synthesized with a 65-nm standard-cell library. The estimation error for the adder is also within the modeling accuracy of 5%, whereas the original logical-effort model and the synthesis timing libraries have errors of up to 40% and 20%, respectively.