Delay analysis of CMOS gates using modified logical effort model

Authors:
A. Kabbani;D. Al-Khalili;A. J. Al-Khalili
Affiliations:
Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, Ont., Canada;-;-
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2006

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Abstract

In this paper, modified logical effort (MLE) technique is proposed to provide delay estimation for CMOS gates. The model accounts for the behavior of series-connected MOSFET structure (SCMS), the input transition time, and internodal charges. Also, the model takes into account deep submicron effects, such as mobility degradation and velocity saturation. This model exhibits good accuracy when compared with Spectre simulations based on BSIM3v3 model. Using UMC's 0.13-μm and TSMC's 0.18-μm technologies, the model has an average error of 4.5% and a maximum error of 15%.