Logical effort: designing for speed on the back of an envelope
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
A unified design methodology for CMOS tapered buffers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Interconnect Effort - A Unification of Repeater Insertion and Logical Effort
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Post-layout logic duplication for synthesis of domino circuits with complex gates
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Logic gates as repeaters (LGR) for area-efficient timing optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Delay analysis of CMOS gates using modified logical effort model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Logical effort model extension to propagation delay representation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The unified logical effort (ULE) model for delay evaluation and minimization in paths composed of CMOS logic gates and resistive wires is presented. The method provides conditions for timing optimization while overcoming the limitations of standard logical effort (LE) in the presence of interconnects. The condition for optimal gate sizing in a logic path with long wires is also presented. This condition is achieved when the delay component due to the gate input capacitance is equal to the delay component due to the effective output resistance of the gate. The ULE delay model unifies the problems of gate sizing and repeater insertion: In the case of negligible interconnect, the ULE method converges to standard LE optimization, yielding tapered gate sizes. In the case of long wires, the solution converges toward uniform sizing of gates and repeaters. The technique is applied to various types of logic paths to demonstrate the influence of wire length, gate type, and technology.