Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
Proceedings of the 41st annual Design Automation Conference
Wave-pipelined on-chip global interconnect
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Timing optimization in logic with interconnect
Proceedings of the 2008 international workshop on System level interconnect prediction
A data capturing method for buses on chip
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Interconnects are assuming increasing importance in deep submicron design, however there is a signicant gap between industrial design practice and classical results of uniform repeater insertion. This work questions two of the standard assumptions of academic interconnect circuits: 1) the uniformity of repeater sizes and spacing and 2) the boundary between logic and interconnects. This research explores the co-design of logic sizing and repeater insertion for improved delay, power and placement. The technique of logical effort is used to develop the sizing scheme for the logic including polarity considerations. Non-uniform repeater insertion is used to c ombine cascade d sizing and distributed wire buffering. HSPICE simulations carried out for the 0:18µ technology show that combining the sized logic with uniform repeaters is faster than using minimum sized logic circuitry by about 10% while with non-uniform repeaters the gain is about 15%. The average power consumption of non-uniform repeater insertion is less than that of uniform insertion by about 20%. Non-uniform repeater insertion is also less placement sensitive (shifting the position of each repeater in the setup by about 40% results in a delay loss of only about 3% while for uniform repeaters the delay loss is about 20%).