Postlayout optimization for synthesis of Domino circuits

Authors:
Aiqun Cao;Ruibing Lu;Chen Li;Cheng-Kok Koh
Affiliations:
Synopsys, Inc., Mountain View, CA;Synopsys, Inc., Mountain View, CA;Purdue University, West Lafayette, IN;Purdue University, West Lafayette, IN
Venue:
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Year:
2006

Citing 9
Cited 0

Logic optimization by output phase assignment in dynamic logic synthesis

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Technology mapping for domino logic

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Automated phase assignment for the synthesis of low power domino circuits

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A performance-driven standard-cell placer based on a modified force-directed algorithm

Proceedings of the 2001 international symposium on Physical design
Design Issues in Mixed Static-Domino Circuit Implementations

ICCD '98 Proceedings of the International Conference on Computer Design
Post-layout logic optimization of domino circuits

Proceedings of the 41st annual Design Automation Conference
Fractional Cut: Improved Recursive Bisection Placement

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Post-layout logic duplication for synthesis of domino circuits with complex gates

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Domino logic synthesis based on implication graph

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.01

Visualization

Abstract

Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this article, we propose a synthesis scheme to reduce the duplication cost by allowing inverters in Domino logic under certain timing constraints for both simple and complex gates. Moreover, we can include the logic duplication minimization during technology mapping for synthesis of Domino circuits with complex gates. In order to guarantee the robustness of such Domino circuits, we perform the logic optimization as a postlayout step. Experimental results show significant reduction in duplication cost, which translates into significant improvements in area and power. As a byproduct, the timing performance is also improved owing to smaller layout area and/or logic depth.