VLSI cell placement techniques
ACM Computing Surveys (CSUR)
Logic synthesis using Synopsys (2nd ed.)
Logic synthesis using Synopsys (2nd ed.)
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
VISI Physical Design Automation: Theory and Practice
VISI Physical Design Automation: Theory and Practice
A force-directed macro-cell placer
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
The placement problem as viewed from the physics of classical mechanics
DAC '75 Proceedings of the 12th Design Automation Conference
Min-max placement for large-scale timing optimization
Proceedings of the 2002 international symposium on Physical design
Timing driven force directed placement with physical net constraints
Proceedings of the 2003 international symposium on Physical design
Benchmarking for large-scale placement and beyond
Proceedings of the 2003 international symposium on Physical design
Timing-driven placement using design hierarchy guided constraint generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Force directed mongrel with physical net constraints
Proceedings of the 40th annual Design Automation Conference
Quadratic placement using an improved timing model
Proceedings of the 41st annual Design Automation Conference
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool
Proceedings of the 2005 international workshop on System level interconnect prediction
An analytic placer for mixed-size placement and timing-driven placement
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Timing-driven placement based on monotone cell ordering constraints
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Postlayout optimization for synthesis of Domino circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We propose a performance-driven cell placement method based on a modified force-directed approach. A pseudo net is added to link the source and sink flip-flops of every critical path to enforce their closeness. Given user-specified I/O pad locations at the chip boundaries and starting with all core cells in the chip center, we iteratively move a cell to its force-balanced location assuming all other cells are fixed. The process stops when no cell can be moved farther than a threshold distance. Next, cell rows are adjusted one at a time starting from the top and bottom. After forming these two rows (top/bottom), all movable core cells force-balanced locations are updated. The row-formation-and-update process continues until all rows are adjusted and, hence, a legal placement is obtained. We have integrated the proposed approach into an industrial APR flow. Experimental results on benchmark circuits up to 191K-cell (500K-gate) show that the critical path delay can be improved by as much as 11.5%. We also study the effect on both layout quality and CPU time consumption due to the amount of pseudo net added. We found that the introduction of pseudo net indeed significantly improves the layout quality.