Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Wireplanning in logic synthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Performance driven multiway partitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A performance-driven standard-cell placer based on a modified force-directed algorithm
Proceedings of the 2001 international symposium on Physical design
Timing driven placement using physical net constraints
Proceedings of the 38th annual Design Automation Conference
Min-max placement for large-scale timing optimization
Proceedings of the 2002 international symposium on Physical design
Timing driven force directed placement with physical net constraints
Proceedings of the 2003 international symposium on Physical design
Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning
Proceedings of the 2003 international symposium on Physical design
Timing-driven placement using design hierarchy guided constraint generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Multi-objective circuit partitioning for cutsize and path-based delay minimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Timing optimization of FPGA placements by logic replication
Proceedings of the 40th annual Design Automation Conference
Multilevel global placement with retiming
Proceedings of the 40th annual Design Automation Conference
Force directed mongrel with physical net constraints
Proceedings of the 40th annual Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Boosting: Min-Cut Placement with Improved Signal Delay
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the 2004 international symposium on Physical design
Modeling repeaters explicitly within analytical placement
Proceedings of the 41st annual Design Automation Conference
An approach to placement-coupled logic replication
Proceedings of the 41st annual Design Automation Conference
Incremental Placement for Timing Optimization
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Sleep transistor distribution in row-based MTCMOS designs
Proceedings of the 17th ACM Great Lakes symposium on VLSI
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In this paper, we present a new timing-driven placement algorithm, which attempts to minimize zigzags and crisscrosses on the timing-critical paths of a circuit. We observed that most of the paths that cause timing problems in the circuit meander outside the minimum bounding box of the start and end nodes of the path. To limit this undesirable behavior, we impose a physical constraint on the placement problem, i.e., we assign a preferred signal direction to each critical path in the circuit. Starting from an initial placement solution, by using a move-based optimization strategy, these preferred directions force cells to move in a direction that maximizes the monotonic behavior of the timing-critical paths in the new placement solution. To make the direction assignment tractable, we implicitly group all circuit paths into a set of input-output conduits and assign a unique preferred direction to each such conduit. We integrated this idea into a recursive bipartitioning-based placement framework with a min-cut objective function. Experimental results on a set of standard placement benchmarks show that-this approach improves the result of a state-of-the-art industrial placement tool for all the benchmark circuits while increasing the wire length by a tolerable amount.