A new retiming-based technology mapping algorithm for LUT-based FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Integrating logic retiming and register placement
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Simultaneous circuit partitioning/clustering with retiming for performance optimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Performance driven multi-level and multiway partitioning with retiming
Proceedings of the 37th Annual Design Automation Conference
Integrated retiming and placement for field programmable gate arrays
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Physical hierarchy generation with routing congestion control
Proceedings of the 2002 international symposium on Physical design
Physical planning with retiming
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Placement driven retiming with a coupled edge timing model
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A novel net weighting algorithm for timing-driven placement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Continuous retiming: algorithms and applications
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Optimal clock period clustering for sequential circuits with retiming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient algorithm for performance-optimal FPGA technology mapping with retiming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-chip communication design: roadblocks and avenues
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Architecture-level synthesis for automatic interconnect pipelining
Proceedings of the 41st annual Design Automation Conference
Retiming for Wire Pipelining in System-On-Chip
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Performance-driven global placement via adaptive network characterization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Physical placement driven by sequential timing analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Timing-driven placement based on monotone cell ordering constraints
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An efficient retiming algorithm under setup and hold constraints
Proceedings of the 43rd annual Design Automation Conference
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous designs, this requires retiming and pipelining on global interconnects. In this paper, we present a practical solution for simultaneous retiming and multilevel global placement for performance optimization, based on the theory and algorithms of sequential timing analysis (Seq-TA). We extend the Seq-TA to handle gates/clusters with multiple outputs and integrate it into a multilevel optimization framework for simultaneous retiming and placement. We also develop two speed-up techniques which enable the Seq-TA to be efficiently integrated into a simulated annealing-based multilevel coarse placement for large-scale designs. Experimental results show that (i) retiming can improve the performance (delay) by 14% on average when it is applied after placement; (ii) our approach for simultaneous retiming and placement can outperform the two-step approach (placement followed by retiming) by 10% on average in terms of delay minimization.