Gate level multiple supply voltage assignment algorithm for power optimization under timing constraint

Authors:
Jun Cheng Chi;Hung Hsie Lee;Sung Han Tsai;Mely Chen Chi
Affiliations:
Department of Electronic Engineering, Chung Yuan Christian University, Chung Li, Taiwan;Department of Information and Computer Engineering, Chung Yuan Christian University, Chung Li, Taiwan;Department of Information and Computer Engineering, Chung Yuan Christian University, Chung Li, Taiwan;Department of Information and Computer Engineering, Chung Yuan Christian University, Chung Li, Taiwan
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2007

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Abstract

We propose a multiple supply voltage scaling algorithm for low power designs. The algorithm combines a greedy approach and an iterative improvement optimization approach. In phase I, it simultaneously scales down as many gates as possible to lower supply voltages. In phase II, a multiple way partitioning algorithm is applied to further refine the supply voltage assignment of gates to reduce the total power consumption. During both phases, the timing correctness of the circuit is maintained. Level converters (LCs) are adjusted correctly according to the local connectivity of the different supply voltage driven gates. Experimental results show that the proposed algorithm can effectively convert the unused slack of gates into power savings. We use two of the ISPD2001 benchmarks and all of the ISCAS89 benchmarks as test cases. The 0.13-µm CMOS TSMC library is used. On average, the proposed algorithm improves the power consumption of the original design by 42.5% with a 10.6% overhead in the number of LCs. Our study shows that the key factor in achieving power saving is including the most comportable supply voltage in the scaling process.