Logic optimization by output phase assignment in dynamic logic synthesis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Automated phase assignment for the synthesis of low power domino circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Design Issues in Mixed Static-Domino Circuit Implementations
ICCD '98 Proceedings of the International Conference on Computer Design
Fractional Cut: Improved Recursive Bisection Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Domino logic synthesis based on implication graph
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-layout logic duplication for synthesis of domino circuits with complex gates
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Postlayout optimization for synthesis of Domino circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this paper, we propose a synthesis scheme to reduce the duplication cost by allowing inverters in Domino logic under certain timing constraints. In order to guarantee the robustness of such Domino circuits, we perform the reduction of logic duplication at the physical level. Experimental results show significant reduction in duplication cost, which translates into significant improvements in area, power, and/or delay.