A novel net-degree distribution model and its application to floorplanning benchmark generation
Integration, the VLSI Journal
Towards layout-friendly high-level synthesis
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
A metric for layout-friendly microarchitecture optimization in high-level synthesis
Proceedings of the 49th Annual Design Automation Conference
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Routability or wiring congestion in a very large scale integration chip is becoming increasingly important as chip complexity increases. Congestion has a significant impact on performance, yield, and chip area. Although advances in placement algorithms have attempted to alleviate this problem, the inherent structure of the logic netlist has a significant impact on the routability irrespective of the placement algorithm used. Placement algorithms find optimal assignments of locations to the logic and do not have the ability to change the netlist structure. Significant decisions regarding the circuit structure are made early in synthesis during the technology-independent logic-optimization step. Optimizations in this step use literal count as a metric for optimization and do not adequately capture the intrinsic entanglement of the netlist. Two circuits with identical literal counts may have significantly different congestion characteristics after placement. In this paper, we postulate that a property of the network structure called adhesion can make a significant contribution to routing congestion. We then provide a metric to measure this property. We evaluate the utility of adhesion as measured by this metric to estimate and optimize postrouting congestion early in the design flow. A heuristic for measuring adhesion is evaluated as well.