Fast Boolean optimization by rewiring
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Circuit Optimization by Rewiring
IEEE Transactions on Computers
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Compatible observability don't cares revisited
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Saving Power by Synthesizing Gated Clocks for Sequential Circuits
IEEE Design & Test
Deterministic Clock Gating for Microprocessor Power Reduction
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Power-aware clock tree planning
Proceedings of the 2004 international symposium on Physical design
A robust algorithm for approximate compatible observability don't care (CODC) computation
Proceedings of the 41st annual Design Automation Conference
Interactive presentation: PowerQuest: trace driven data mining for power optimization
Proceedings of the conference on Design, automation and test in Europe
A new paradigm for synthesis and propagation of clock gating conditions
Proceedings of the 45th annual Design Automation Conference
A scalable algorithm for RTL insertion of gated clocks based on ODCs computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinational and sequential logic optimization by redundancy addition and removal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Traditionally, clock gating for power saving is mainly done at Register Transistor Level (RTL), while in a lower logical level some synthesis techniques, e.g. Observability Don't Care (ODC) can also be used to provide more power savings. In this paper, we propose an effective logic level ODC-based clock gating scheme that aims to reduce the intra-module dynamic power of sequential circuits. It is accompanied with a rewiring-based pruning scheme to trim down the incurred area overhead. Switching activity is put into account in the optimization processes. Extensive experimental results obtained by using ModelSim and PowerCompiler on the ISCAS-89 benchmarks showed that without rewired area trimming, an average of 40% on clock power and 12% on total dynamic power can be saved with a total cell area overhead of 6%. When rewiring was applied to trim down the area overhead, a similar clock power saving of 40% and an appealing 17% of total dynamic power saving can be achieved with area similar (-1%) to the original non ODC-clock-gated circuits.