Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages

Authors:
M. Hrkic;J. Lillis
Affiliations:
Dept. of Comput. Sci., Univ. of Illinois, Chicago, IL, USA;-
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2006

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Abstract

We give an overview of a buffer tree synthesis package which pays particular attention to the following issues: routing and buffer blockages, minimization of interconnect and buffer costs, congestion, exploitation of temporal locality among the sinks, and addressing sink polarity requirements. Experimental results demonstrate the effectiveness of the tool in comparison with previously proposed techniques.