Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration

Authors:
Yibo Wang;Yici Cai;Xianlong Hong;Yi Zou
Affiliations:
-;-;-;-
Venue:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Year:
2007

Citing 8
Cited 0

A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A simultaneous routing tree construction and fanout optimization algorithm

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Buffer insertion with accurate gate and interconnect delay computation

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A graph based algorithm for optimal buffer insertion under accurate delay models

Proceedings of the conference on Design, automation and test in Europe
A fast and accurate delay estimation method for buffered interconnects

Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Buffer insertion plays a great role in modern global interconnect optimization. But too many buffers exhaust routing resources, and result in the rise of the power dissipation. Unfortunately, simplified delay models used by most of the present buffer insertion algorithms may introduce redundant buffers due to the delay estimation errors, whereas accurate delay models expand the solution space significantly, resulting in unacceptable runtime. Moreover, the power dissipation problem becomes a dominant factor in the state-of-the-art IC design. Not only transistor but also interconnect should be taken into consideration in the power calculation, which makes us have to use an accurate power model to calculate the total power dissipation. In this paper, we present two stochastic optimization methods, simulated annealing and solution space smoothing, which use accurate delay and power models to construct buffered routing trees with considerations of buffer/wire sizing, routing obstacles and delay and power optimization. Experimental results show our methods can save much of the buffer area and the power dissipation with better solutions, and for the cases with pins ≤ 15, the runtime of solution space smoothing is tens of times faster.