Logical effort: designing for speed on the back of an envelope
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Timing driven placement using complete path delays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A methodology and algorithms for post-placement delay optimization
DAC '94 Proceedings of the 31st annual Design Automation Conference
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multilevel circuit partitioning
DAC '97 Proceedings of the 34th annual Design Automation Conference
Layout driven re-synthesis for low power consumption LSIs
DAC '97 Proceedings of the 34th annual Design Automation Conference
Unification of budgeting and placement
DAC '97 Proceedings of the 34th annual Design Automation Conference
An exact solution to simultaneous technology mapping and linear placement problem
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Timing driven placement in interaction with netlist transformations
Proceedings of the 1997 international symposium on Physical design
Design methodology for the S/390 parallel enterprise server G4 microprocessors
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Timing metrics for physical design of deep submicron technologies
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Gate-size selection for standard cell libraries
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
An integrated placement and synthesis approach for timing closure of PowerPC/sup TM/ microprocessors
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Performance Driven Optimization of Network Length in Physical Placement
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Faster minimization of linear wirelength for global placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and accurate wire delay estimation for physical synthesis of large ASICs
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Logical and physical design: a flow perspective
Logic Synthesis and Verification
Congestion aware layout driven logic synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Understanding metrics in logic synthesis for routability enhancement
Proceedings of the 2003 international workshop on System-level interconnect prediction
Benchmarking for large-scale placement and beyond
Proceedings of the 2003 international symposium on Physical design
Porosity aware buffered steiner tree construction
Proceedings of the 2003 international symposium on Physical design
Design topology aware physical metrics for placement analysis
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Free space management for cut-based placement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Physical synthesis methodology for high performance microprocessors
Proceedings of the 40th annual Design Automation Conference
Designing mega-ASICs in nanogate technologies
Proceedings of the 40th annual Design Automation Conference
Pushing ASIC performance in a power envelope
Proceedings of the 40th annual Design Automation Conference
Fast Comparisons of Circuit Implementations
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Sensitivity guided net weighting for placement driven synthesis
Proceedings of the 2004 international symposium on Physical design
Sensitivity guided net weighting for placement driven synthesis
Proceedings of the 2004 international symposium on Physical design
Issues and strategies for the physical design of system-on-a-chip ASICs
IBM Journal of Research and Development
A Mask Reuse Methodology for Reducing System-on-a-Chip Cost
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Proceedings of the 2005 international symposium on Physical design
Improving run times by pruned application of synthesis transforms
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Logical effort based technology mapping
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
SafeResynth: A new technique for physical synthesis
Integration, the VLSI Journal
Path smoothing via discrete optimization
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Fast comparisons of circuit implementations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |