Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Simultaneous gate sizing and fanout optimization
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Design topology aware physical metrics for placement analysis
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Geometric programming for circuit optimization
Proceedings of the 2005 international symposium on Physical design
Floorplan management: incremental placement for gate sizing and buffer insertion
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Digital Circuit Optimization via Geometric Programming
Operations Research
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Path smoothing via discrete optimization
Proceedings of the 45th annual Design Automation Conference
A fuzzy optimization approach for variation aware power minimization during gate sizing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Incremental buffer insertion and module resizing algorithm using geometric programming
Proceedings of the 19th ACM Great Lakes symposium on VLSI
ITOP: integrating timing optimization within placement
Proceedings of the 19th international symposium on Physical design
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This paper presents an iterative optimization technique for improving delay in integrated circuits. The basic idea is to perform timing analysis to identify the set of k most-critical paths in the circuit followed by cell resizing and replacement along the critical path set and their neighboring cells. The process is repeated until no further reduction in circuit delay is possible. At the core of this technique lies a mathematical formulation for simultaneous cell sizing and placement subject to timing and position constraints. We show that the resulting problem formulation is a generalized geometric program, which can be solved by solving a sequence of geometric programs. Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches which separate gate sizing from gate placement